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? 2002 microchip technology inc. ds21189e-page 1 m 24aa64/24lc64 device selection table features ? single supply with operation down to 1.8v ? low power cmos technology - 1 ma active current typical - 1 a standby current (max.) (i-temp) ? organized as 8 blocks of 8k bit (64k bit) ? 2-wire serial interface bus, i 2 c? compatible ? cascadable for up to eight devices ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz (24aa64) and 400 khz (24lc64) com- patibility ? self-timed write cycle (including auto-erase) ? page-write buffer for up to 32 bytes ? 2 ms typical write cycle time for page-write ? hardware write protect for entire memory ? can be operated as a serial rom ? factory programming (qtp) available ? esd protection > 4,000v ? 1,000,000 erase/write cycles ? data retention > 200 years ? 8-lead pdip, soic, tssop, and msop package ? available temperature ranges: description the microchip technology inc. 24aa64/24lc64 (24xx64*) is a 64 kbit electrically erasable prom. the device is organized as eight blocks of 1k x 8-bit memory with a 2-wire serial interface. low voltage design permits operation down to 1.8v with standby and active currents of only 1 a and 1 ma respectively. it has been developed for advanced, low power appli- cations such as personal communications or data acquisition. the 24xx64 also has a page-write capabil- ity for up to 32 bytes of data. functional address lines allow up to eight devices on the same bus, for up to 512 kbits address space. the 24xx64 is available in the standard 8-pin pdip, surface mount soic, tssop and msop packages. package types block diagram part number v cc range max clock frequency temp ranges 24aa64 1.8-5.5 400 khz (1) i 24lc64 2.5-5.5 400 khz i, e note 1: 100 khz for v cc <2.5v - industrial (i): -40c to +85c - automotive (e): -40c to +125c 24xx64 a0 a1 a2 vss 1 2 3 4 8 7 6 5 vcc wp scl sda pdip/soic/tssop/msop 24xx64x wp vcc a0 a1 scl sda vss a2 1 2 3 4 8 7 6 5 rotated tssop (24aa64x/24lc64x) hv generator eeprom array page latches ydec xdec sense amp r/w control i/o control logic i/o memory control logic a0 a1 wp a2 scl sda v cc v ss 64k i 2 c ? serial eeprom *24xx64 is used in this document as a generic part number for the 24aa64/24lc64 devices.
24aa64/24lc64 ds21189e-page 2 ? 2002 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings? v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temp. with power applied ............................................................................................... ...........-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv 1.1 dc c haracteristics ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics v cc = +1.8v to +5.5v industrial (i): t amb = -40c to +85c automotive (e): t amb = -40c to +125c param. no. sym characteristic min typ max units conditions d1 v ih wp, scl and sda pins ? ???? d2 ? high level input voltage 0.7 v cc ??v? d3 v il low level input voltage ? ? 0.3 v cc v? d4 v hys hysteresis of schmitt trigger inputs 0.05 v cc ??v (note 1) d5 v ol low level output voltage ? ? 0.40 v i ol = 3.0 ma, v cc = 2.5v d6 i li input leakage current ??10av in =.1v to v cc d7 i lo output leakage current ??10av out =.1v to v cc d8 c in , c out pin capacitance (all inputs/outputs) ? ? 10 pf v cc = 5.0v (note 1) t amb = 25c, f clk = 1 mhz d9 i cc write operating current ?0.1 3mav cc = 5.5v, scl = 400 khz d10 i cc read ? 0.05 1 ma ? d11 i ccs standby current ? ? .01 ? 1 5 a a industrial automotive sda = scl = v cc wp = v ss note 1: this parameter is periodically sampled and not 100% tested. 2: typical measurements taken at room temperature.
? 2002 microchip technology inc. ds21189e-page 3 24aa64/24lc64 1.2 ac c haracteristics ac characteristics v cc = +1.8v to +5.5v industrial (i): t amb = -40c to +85c automotive (e): t amb = -40c to +125c param. no. sym characteristic min max units conditions 1f clk clock frequency ? ? 400 100 khz 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 2 t high clock high time 600 4000 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 3t low clock low time 1300 4700 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 4t r sda and scl rise time (note 1) ? ? 300 1000 ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 5t f sda and scl fall time ? 300 ns (note 1) 6t hd : sta start condition hold time 600 4000 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 7t su : sta start condition setup time 600 4700 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 8t hd : dat data input hold time 0 ? ns (note 2) 9t su : dat data input setup time 100 250 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 10 t su : sto stop condition setup time 600 4000 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 11 t aa output valid from clock (note 2) ? ? 900 3500 ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 12 t buf bus free time: time the bus must be free before a new transmission can start 1300 4700 ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa64) 13 t of output fall time from v ih min- imum to v il maximum 20+0.1c b ? 250 250 ns 2.5v v cc 5.5v 1.8v v cc 2.5v (24aa64) 14 t sp input filter spike suppression (sda and scl pins) ?50ns (notes 1 and 3) 15 t wc write cycle time (byte or page) ?5ms? 16 ? endurance 1m ? cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on microchip?s website: www.microchip.com.
24aa64/24lc64 ds21189e-page 4 ? 2002 microchip technology inc. figure 1-1: bus timing data figure 1-2: bus timing start/stop 7 5 2 4 8 910 12 11 14 6 scl sda in sda out 3 7 6 d4 10 start stop scl sda
? 2002 microchip technology inc. ds21189e-page 5 24aa64/24lc64 2.0 functional description the 24xx64 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24xx64 works as slave. both master and slave can operate as trans- mitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last six- teen will be stored when doing a write operation. when an overwrite does occur it will replace data in a first-in first-out (fifo) fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges, has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx64) will leave the data line high to enable the master to generate the stop con- dition. figure 3-1: data transfer sequence on the serial bus note: the 24xx64 does not generate any acknowledge bits if an internal program- ming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
24aa64/24lc64 ds21189e-page 6 ? 2002 microchip technology inc. 3.6 device addressing a control byte is the first byte received following the start condition from the master device (figure 3-2). the control byte consists of a four bit control code; for the 24xx64 this is set as 1010 binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xx64 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1, and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. the next two bytes received define the address of the first data byte (figure 3-3). because only a12...a0 are used, the upper three address bits are don?t care bits. the upper address bits are trans- ferred first, followed by the less significant bits. following the start condition, the 24xx64 monitors the sda bus checking the device type identifier being transmitted. upon receiving a 1010 code and appropri- ate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx64 will select a read or write operation. figure 3-2: control byte format 3.7 contiguous addressing across multiple devices the chip select bits a2, a1, a0 can be used to expand the contiguous address space for up to 512k bits by adding up to eight 24xx64's on the same bus. in this case, software can use a0 of the control byte as address bit a13, a1 as address bit a14, and a2 as address bit a15. it is not possible to sequentially read across device boundaries. figure 3-3: address sequence bit assignments 1 0 1 0 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit 1010 a 2 a 1 a 0 r/w xxx a 11 a 10 a 9 a 7 a 0 a 8 ?????? a 12 control byte address high byte address low byte control code chip select bits x = don?t care bit
? 2002 microchip technology inc. ds21189e-page 7 24aa64/24lc64 4.0 write operations 4.1 byte write following the start condition from the master, the control code (four bits), the chip select (three bits), and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmit- ted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx64. the next byte is the least significant address byte. after receiving another acknowledge sig- nal from the 24xx64 the master device will transmit the data word to be written into the addressed memory location. the 24xx64 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24xx64 will not generate acknowledge signals (figure 4-1). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. after a byte write command, the internal address counter will point to the address location following the one that was just written. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24xx64 in the same way as in a byte write. but instead of generating a stop condi- tion, the master transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. after receipt of each word, the five lower address pointer bits are internally incre- mented by one. if the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an inter- nal write cycle will begin (figure 4-2). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. 4.3 write protection the wp pin allows the user to write protect the entire array (0000-1fff) when the pin is tied to v cc . if tied to v ss or left floating, the write protection is disabled. the wp pin is sampled at the stop bit for every write com- mand (figure 3-1) toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. note: page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actu- ally being written. physical page bound- aries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (over- writing data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
24aa64/24lc64 ds21189e-page 8 ? 2002 microchip technology inc. figure 4-1: byte write figure 4-2: page write xxx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data s t o p a c k a c k a c k a c k x = don?t care bit s1010 0 a 2 a 1 a 0 p xxx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 s t o p a c k a c k a c k a c k data byte 31 a c k x = don?t care bit s101 0 0 a 2 a 1 a 0 p
? 2002 microchip technology inc. ds21189e-page 9 24aa64/24lc64 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack w ill be returned. if no ack is returned, then the start bit and control byte must be re-sent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
24aa64/24lc64 ds21189e-page 10 ? 2002 microchip technology inc. 6.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the control byte is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 6.1 current address read the 24xx64 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. upon receipt of the control byte with r/w bit set to one, the 24xx64 issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24xx64 discontinues transmission (figure 6-1). 6.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24xx64 as part of a write operation (r/w bit set to 0). after the word address is sent, the master generates a start condition following the acknowledge. this termi- nates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24xx64 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition which causes the 24xx64 to discontinue transmission (figure 6-2). after a random read command, the inter- nal address counter will point to the address location following the one that was just read. 6.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24xx64 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx64 to transmit the next sequentially addressed 8-bit word (figure 6-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will gen- erate a stop condition. to provide sequential reads the 24xx64 contains an internal address pointer which is incremented by one at the completion of each opera- tion. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 1fff to address 0000 if the master acknowl- edges the byte received from the array address 1fff. figure 6-1: current address read sp bus activity master sda line bus activity s t o p control byte data (n) a c k n o a c k s t a r t
? 2002 microchip technology inc. ds21189e-page 11 24aa64/24lc64 figure 6-2: random read figure 6-3: sequential read xxx bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte address high byte address low byte control byte data byte s t a r t x = don?t care bit s1010 aaa 0 210 s1 0 1 0 aaa 1 210 p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p
24aa64/24lc64 ds21189e-page 12 ? 2002 microchip technology inc. 7.0 pin descriptions the descriptions of the pins are listed in table 7-1. table 7-1: pin function table 7.1 a0, a1, a2 chip address inputs the a0,a1,a2 inputs are used by the 24xx64 for mul- tiple device operation. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v cc or v ss . 7.2 serial data (sda) this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open- drain terminal, therefore, the sda bus requires a pullup resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz) for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 7.3 serial clock (scl) this input is used to synchronize the data transfer from and to the device. 7.4 write protect (wp) this pin can be connected to either v ss , v cc or left floating. an internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. if tied to v ss or left floating, normal memory operation is enabled (read/write the entire memory 0000-1fff). if tied to v cc , write operations are inhibited. read operations are not affected. name pdip soic tssop msop rotated tssop description a0 1 1 1 1 3 chip address input a1 2 2 2 2 4 chip address input a2 3 3 3 3 5 chip address input v ss 4 4 4 4 6 ground sda 5 5 5 5 7 serial address/data i/o scl 6 6 6 6 8 serial clock wp 7 7 7 7 1 write protect input v cc 8 8 8 8 2 +1.8v to 5.5v power supply
? 2002 microchip technology inc. ds21189e-page 13 24aa64/24lc64 8.0 packaging information 8.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn 8-lead tssop example: 24lc64 i/pnnn yyww 24lc64 i/snyyww nnn xxxx xyww nnn 4l64 iyww nnn legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, and traceability code. 8-lead msop example: xxxxxx ywwnnn 4l64i ywwnnn 8-lead soic (208 mil) example: xxxxxxxx xxxxxxxx yywwnnn 24lc64 i/sm yywwnnn rotated tssop marking will be ?4lbx?
24aa64/24lc64 ds21189e-page 14 ? 2002 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2002 microchip technology inc. ds21189e-page 15 24aa64/24lc64 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle f 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 f a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
24aa64/24lc64 ds21189e-page 16 ? 2002 microchip technology inc. 8-lead plastic small outline (sm) ? medium, 208 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.43 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.64 0.51 .030 .025 .020 l foot length 5.33 5.21 5.13 .210 .205 .202 d overall length 5.38 5.28 5.11 .212 .208 .201 e1 molded package width 8.26 7.95 7.62 .325 .313 .300 e overall width 0.25 0.13 0.05 .010 .005 .002 a1 standoff 1.98 .078 a2 molded package thickness 2.03 .080 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 a a1 l c 2 1 d n p b e e1 .070 .075 .069 .074 1.78 1.75 1.97 1.88 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. drawing no. c04-056 significant characteristic
? 2002 microchip technology inc. ds21189e-page 17 24aa64/24lc64 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c f 1 2 d n p b e e1 foot angle f 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
24aa64/24lc64 ds21189e-page 18 ? 2002 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) p a a1 a2 d l c dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 .035 f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b 7 7 .004 .010 0 .006 .012 (f) dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .114 .114 .022 .118 .118 .002 .030 .193 .034 min p n units .026 nom 8 inches 1.00 0.95 0.90 .039 0.15 0.30 .008 .016 6 0.10 0.25 0 7 7 0.20 0.40 6 millimeters* 0.65 0.86 3.00 3.00 0.55 4.90 .044 .122 .028 .122 .038 .006 0.40 2.90 2.90 0.05 0.76 min max nom 1.18 0.70 3.10 3.10 0.15 0.97 max 8 e1 e b n 1 2 significant characteristic .184 .200 4.67 .5.08
? 2002 microchip technology inc. ds21189e-page 19 24aa64/24lc64 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events 013001
24aa64/24lc64 ds21189e-page 20 ? 2002 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21189e 24aa64/24lc64
? 2002 microchip technology inc. ds21189e-page21 24aa64/24lc64 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: 24aa64: 1.8v, 64 kbit i 2 c serial eeprom 24aa64t: 1.8v, 64 kbit i 2 c serial eeprom (tape and reel) 24aa64x 1.8v, 64 kbit i 2 c serial eeprom in alternate pinout (st only) 24aa64xt 1.8v, 64 kbit i 2 c serial eeprom in alternate pinout (st only) 24lc64: 2.5v, 64 kbit i 2 c serial eeprom 24lc64t: 2.5v, 64 kbit i 2 c serial eeprom (tape and reel) 24lc64x 2.5v, 64 kbit i 2 c serial eeprom in alternate pinout (st only) 24lc64xt 2.5v, 64 kbit i 2 c serial eeprom in alternate pinout (st only) temperature range: i = -40c to +85c e = -40c to +125c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead st = plastic tssop (4.4 mm), 8-lead ms = plastic micro small outline (msop), 8-lead examples: a) 24aa64-i/p: industrial temperature, pdip package b) 24aa64-i/sn: industrial temperature, soic package c) 24aa64-i/sm: industrial temperature, soic (208 mil) package d) 24aa64x-i/st: industrial temperature, rotated tssop package a) 24lc64-i/p: industrial temperature, pdip package b) 24lc64-e/sn: extended temperature, soic package c) 24lc64-e/sm: extended temperature, soic (208 mil) package d) 24lc64x-i/st : extended temperature, rotated tssop package
24aa64/24lc64 ds21189e-page 22 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21189e - page 23 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microid, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21189e-page 24 ? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 ta iw a n microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/18/02 *ds21189e* w orldwide s ales and s ervice

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